View LTC1344-15_9071186.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ltc1344 software-selectable cable terminator n software-selectable cable termination for: rs232 (v.28) rs423 (v.10) rs422 (v.11) rs485 rs449 eia530 eia530-a v.35 v.36 x.21 n outputs wont load the line with power off the ltc ? 1344 features six software-selectable multiprotocol cable terminators. each terminator can be configured as an rs422 (v.11) 100 w minimum differen- tial load, v.35 t-network load or an open circuit for use with rs232 (v.28) or rs423 (v.10) transceivers that provide their own termination. when combined with the ltc1343, the ltc1344 forms a complete software-select- able multiprotocol serial port. a data bus latch feature allows sharing of the select lines between multiple inter- face ports. the ltc1344 is available in a 24-lead ssop. daisy-chained control outputs n data networking n csu and dsu n data routers , ltc and lt are registered trademarks of linear technology corporation. d2 ltc1343 rts dtr dsr dcd cts rl d1 d3 d4 r1 r3 r4 r2 d2 ltc1343 ll txd scte txc rxc rxd tm ll a (141) txd a (103) txd b scte a (113) scte b rxc a (115) rxc b rxd a (104) rxd b rts a (105) rts b dtr a (108) dtr b cts a (106) cts b tm a (142) sgnd (102) shield (101) 18 2 14 24 11 15 12 17 9 3 1 4 19 20 23 6 22 8 10 5 13 21 7 16 25 1344 ta01 db-25 connector ltc1344 d1 d3 d4 r1 r3 r4 r2 txc a (114) txc b rl a (140) dcd a (109) dcd b dsr a (107) dsr b features descriptio u applicatio s u typical applicatio n u
2 ltc1344 absolute m axi m u m ratings w ww u wu u package / o rder i for atio order part number ltc1344cg ltc1344ig 1 2 3 4 5 6 7 8 9 10 11 12 top view g package 24-lead plastic ssop 24 23 22 21 20 19 18 17 16 15 14 13 m0 v ee r1c r1b r1a r2a r2b r2c r3a r3b r3c gnd m1 m2 dce/dte latch r6b r6a r5a r5b r4a r4b v cc gnd t jmax = 150 c, q ja = 100 c/w consult factory for military grade parts. electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 . v cc = 5v 5%, v ee = C5v 5%, t a = t min to t max (notes 2, 3) unless otherwise noted. symbol parameter conditions min typ max units supplies i cc supply current all digital pins = gnd or v cc l 200 700 m a terminator pins r v.35 differential mode impedance all loads (figure 1), C 2v v cm 2v (commercial) l 90 103 110 w common mode impedance all loads (figure 2), C 2v v cm 2v (commercial) l 135 153 165 w all loads (figure 1), C 2v v cm 2v (industrial) l 90 104 125 w all loads (figure 2), C 2v v cm 2v (industrial) l 130 153 170 w r v.11 differential mode impedance all loads (figure 1), C 7v v cm 7v (commercial) 100 104 w all loads (figure 1), v cm = 0v (commercial) l 100 104 110 w all loads (figure 1), v cm = 0v (industrial) l 95 104 125 w i leak high impedance leakage current all loads, C 7v v cm 7v (commercial) l 1 50 m a logic inputs v ih input high voltage all logic input pins l 2v v il input low voltage all logic input pins l 0.8 v i in input current all logic input pins l 10 m a note 3: all typicals are given at v cc = 5v, v ee = C 5v, t a = 25 c. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are reference to ground unless otherwise specified. (note 1) positive supply voltage (v cc ) ................................... 7v negative supply voltage (v ee ) ........................... C 13.2v input voltage (logic inputs) .... v ee C 0.3v to v cc + 0.3v input voltage (load inputs) .................................. 18v operating temperature range ltc1344c ............................................... 0 c to 70 c ltc1344i ........................................... C 40 c to 85 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c
3 ltc1344 typical perfor m a n ce characteristics u w v.11 or v.35 differential mode impedance vs common mode voltage temperature ( c) ?0 differential mode impedance ( w ) 20 1344 g01 110 105 ?0 0 40 100 120 115 60 80 100 v cm = ?v v cm = 2v v cm = 0v v cm = 7v v cc voltage (v) 103 differential mode impedance ( w ) 104 105 1344 g03 4.6 4.8 5.0 5.2 5.4 common mode voltage (v) ? differential mode impedance ( w ) 108 6 1344 g02 106 104 100 ? ? 2 0 2 4 8 102 v.11 or v.35 differential mode impedance vs temperature v.35 common mode impedance vs supply voltage (v cc ) v.35 common mode inpedance vs negative supply voltage (v ee ) v cc voltage (v) 151 common mode impedance ( w ) 152 153 1344 g07 4.6 4.8 5.0 5.2 5.4 v ee voltage (v) 5.4 common mode impedance ( w ) 153 154 4.6 1344 g08 152 151 150 5.2 5.0 4.8 supply current vs temperature temperature ( c) ?0 supply current ( m a) 1344 g09 310 290 270 250 230 210 190 170 150 ?0 10 40 70 100 v.11 or v.35 differential mode impedance vs negative supply voltage (v ee ) temperature ( c) ?0 common mode impedance ( w ) 20 1344 g05 155 150 ?0 0 40 145 165 160 60 80 100 v cm = 2v v cm = 2v v cm = 0v common mode voltage (v) ? common mode impedance ( w ) 154 156 2 1344 g06 152 150 ? 0 1 158 v.35 common mode impedance vs temperature v.35 common mode impedance vs common mode voltage v ee voltage (v) 103 differential mode impedance ( w ) 104 105 1344 g04 5.4 5.2 5.0 4.8 4.6 v.11 or v.35 differential mode impedance vs supply voltage (v cc )
4 ltc1344 test circuits pi n fu n ctio n s uuu m0 (pin 1): ttl level mode select input. the data on m0 is latched when latch is high. v ee (pin 2): negative supply voltage input. can connect directly to the ltc1343 v ee pin. r1c (pin 3): load 1 center tap. r1b (pin 4): load 1 node b. r1a (pin 5): load 1 node a. r2a (pin 6): load 2 node a. r2b (pin 7): load 2 node b. r2c (pin 8): load 2 center tap. r3a (pin 9): load 3 node a. r2b (pin 10): load 2 node b. r3c (pin 11): load 3 center tap. gnd (pin 12): ground connection for load 1 to load 3. gnd (pin 13): ground connection for load 4 to load 6. v cc (pin 14): positive supply input. 4.75v v cc 5.25v. r4b (pin 15): load 4 node b. r4a (pin 16): load 4 node a. r5b (pin 17): load 5 node b. r5a (pin 18): load 5 node a. r6a (pin 19): load 6 node a. r6b (pin 20): load 6 node b. latch (pin 21): ttl level logic signal latch input. when it is low the input buffers on m0, m1, m2 and dce/dte are transparent. when it is high the logic pins are latched into their respective input buffers. the data latch allows the select lines to be shared between multiple i/o ports. dce/dte (pin 22): ttl level mode select input. the dce mode is selected when it is high and dte mode when low. the data on dce/dte is latched when latch is high. m2 (pin 23): ttl level mode select input 1. the data on m2 is latched when latch is high. m1 (pin 24): ttl level mode select input 2. the data on m1 is latched when latch is high. r1 51.5 w r2 51.5 w 7v or 2v 1344 f01 r3 124 w s2 off s1 on c v w a b r1 51.5 w r2 51.5 w 2v 1344 f02 r3 124 w s2 on s1 on c v w a, b figure 1. differential v.11 or v.35 impedance measurement figure 2. v.35 common mode impedance measurement
5 ltc1344 ltc1344 mode name dce/dte m2 m1 m0 r1 r2 r3 r4 r5 r6 v.10/rs423 x 000zzzzzz rs530a 0 001zzz v.11 v.11 v.11 1 001zzzz v.11 v.11 reserved 0 010zzz v.11 v.11 v.11 1 0 1 0 v.11 v.11 v.11 z z z x.21 0 011zzz v.11 v.11 v.11 1 011zzzz v.11 v.11 v.35 0 1 0 0 v.35 v.35 z v.35 v.35 v.35 1 1 0 0 v.35 v.35 v.35 z v.35 v.35 rs530/rs449/v.36 0 101zzz v.11 v.11 v.11 1 101zzzz v.11 v.11 v.28/rs232 x 110zzzzzz no cable x 1 1 1 v.11 v.11 v.11 v.11 v.11 v.11 x = dont care, 0 = logic low, 1 = logic high ode selectio w u r1 51.5 w r2 51.5 w r3 124 w s2 off s1 on c v.11 mode v.35 mode hi-z mode a b r1 51.5 w r2 51.5 w r3 124 w s2 on s1 on c a b r1 51.5 w r2 51.5 w 1344 f03 r3 124 w c a b s2 off s1 off figure 3. ltc1344 modes
6 ltc1344 applicatio n s i n for m atio n wu u u multiprotocol cable termination one of the most difficult problems facing the designer of a multiprotocol serial interface is how to allow the trans- mitters and receivers for different electrical standards to share connector pins. in some cases the transmitters and receivers for each interface standard can be simply tied together and the appropriate circuitry enabled. but the biggest problem still remains: how to switch the various cable terminations required by the different standards. traditional implementations have included switching re- sistors with expensive relays or requiring the user to change termination modules every time the interface standard has changed. custom cables have been used with the termination in the cable head or separate termina- tions are built on the board, and a custom cable routes the signals to the appropriate termination. switching the terminations using fets is difficult because the fets must remain off even though the signal voltage is beyond the supply voltage for the fet drivers or the power is off. the ltc1344 solves the cable termination switching prob- lem via software control. the ltc1344 provides termina- tion for the v.10 (rs423), v.11 (rs422), v.28 (rs232) and v.35 electrical protocols. v.10 (rs423) termination a typical v.10 unbalanced interface is shown in figure 4. a v.10 single-ended generator output a with ground c is connected to a differential receiver with inputs a ' con- nected to a and input b ' connected to the signal return ground c. the receivers ground c ' is separate from the signal return. usually no cable termination is required for v.10 interfaces but the receiver inputs must be compliant with the impedance curve shown in figure 5. in v.10 mode, both switches s1 and s2 are turned off so the only cable termination is the input impedance of the v.10 receiver. a cable termination load generator balanced interconnecting cable receiver a ' c b ' c ' 1344 f04 figure 4. typical v.10 interface v.11 (rs422) termination a typical v.11 balanced interface is shown in figure 6. a v.11 differential generator with outputs a and b with ground c is connected to a differential receiver with ground c ' , inputs a ' connected to a, b ' connected to b. the v.11 interface requires a different termination at the re- ceiver end that has a minimum value of 100 w . the receiver inputs must also be compliant with the impedance curve shown in figure 7. in v.11 mode, switch s1 is turned on and s2 is turned off so the cable is terminated with a 103 w impedance. figure 5. v.10 interface using the ltc1344 z z z s2 off 124 w ltc1344 v.10 receiver a b c 1344 f05 51.5 w 51.5 w i z ?v 3v 10v ?0v 3.25ma 3.25ma v z s1 off
7 ltc1344 applicatio n s i n for m atio n wu u u figure 6. typical v.11 interface z z z s1 on s2 off 124 w ltc1344 v.11 receiver a b c 1344 f07 51.5 w 51.5 w i z ?v 3v 10v ?0v 3.25ma 3.25ma v z figure 7. v.11 interface using the ltc1344 v.28 (rs232) termination a typical v.28 unbalanced interface is shown in figure 8. a v.28 single-ended generator output a with ground c is connected to a single-ended receiver with inputs a ' con- nected to a, ground c ' connected via the signal return ground to c. the v.28 standard requires a 5k terminating resistor to ground which is included in almost all compli- ant receivers as shown in figure 9. because the termina- tion is included in the receiver, both switches s1 and s2 in the ltc1344 are turned off. a cable termination load generator balanced interconnecting cable receiver a ' cc ' 1344 f08 figure 8. typical v.28 interface s1 off s2 off 124 w ltc1344 v.28 receiver a b c 1344 f09 51.5 w 51.5 w 5k figure 9. v.28 interface using the ltc1344 v.35 termination a typical v.35 balanced interface is shown in figure 10. a v.35 differential generator with outputs a and b with ground c is connected to a differential receiver with ground c ' , inputs a ' connected to a, b ' connected to b. the v.35 interface requires a t-network termination at the receiver end and the generator end. in v.35 mode both switches s1 and s2 in the ltc1344 are turned on as shown in figure 11. the differential impedance measured at the connector must be 100 w 10 w and the impedance between shorted terminals a ' and b ' to ground c ' must be 150 w 15 w . the input impedance of the v.35 receiver is connected in parallel with the t-network inside the ltc1344, which can cause the overall impedance to fail the specification on the a cable termination load generator balanced interconnecting cable receiver a ' bb ' c ' c 100 w min 1344 f06
8 ltc1344 and b to ground c must be 150 w 15 w . for the generator termination, switches s1 and s2 are both on and the top side of the center resistor is brought out to a pin so it can be bypassed with an external capacitor to reduce common mode noise as shown in figure 12. any mismatch in the driver rise and fall times or skew in the driver propagation delays will force current through the center termination resistor to ground causing a high frequency common mode spike on the a and b terminals. the common mode spike can cause emi problems that are reduced by capacitor c1 which shunts much of the com- mon mode energy to ground rather than down the cable. the latch pin the latch pin (21) allows the select lines (m0, m1, m2 and dce/dte) to be shared with multiple ltc1344s, each with its own latch signal. when the latch pin is held low the select line input buffers are transparent. when the latch pin is pulled high, the select line input buffers latch the state of the select pins so that changes on the select lines are ignored until latch is pulled low again. if the latch feature is not used, the latch pin should be tied to ground. applicatio n s i n for m atio n wu u u a cable termination load generator balanced interconnecting cable receiver a ' 50 w 50 w 125 w b c b ' c ' 1344 f10 125 w 50 w 50 w figure 10. typical v.35 interface z z z s1 on s2 on 124 w ltc1344 v.35 receiver a b c 1344 f11 51.5 w 51.5 w i z ?v 3v 12v ?v 0.8ma 1ma v z figure 11. v.35 receiver using the ltc1344 low side. however, all of linear technologys v.35 receiv- ers meet the rs485 input impedance specification as shown in figure 11, which insures compliance with the v.35 specification when used with the ltc1344. the generator differential impedance must be 50 w to 150 w and the impedance between shorted terminals a s1 on s2 on 124 w ltc1344 v.35 driver a b c 1344 f12 51.5 w 51.5 w c1 100pf figure 12. v.35 driver using the ltc1344
9 ltc1344 typical applicatio n s n u figure 13 shows a typical application for the ltc1344 using the ltc1343 mixed mode transceiver chip to gener- ate the clock and data signals for a serial interface. the ltc1344 v ee supply is generated from the ltc1343 charge pump and the select lines m0, m1, m2, dce and latch are shared by both chips. each driver output and receiver input is connected to one of the ltc1344 termi- nation ports. each electrical protocol can then be chosen using the digital select lines. ltc1343 38 1344 f13 3842 6 7 9 13 14 15 37 36 35 34 33 32 31 30 29 28 27 m0 m1 m2 dce/dte latch 17 18 19 21 22 ltc1344 14 21 22 23 24 1 2 5v 5 3 8 11 12 13 4 6 7 9 10 16 15 18 17 19 20 dte dce txd + rxd + txd rxd rxd + txd + rxd txd scte + txc + scte txc nc rxc + nc rxc rxc + nc rxc nc txc + scte + txc scte v cc v ee m2 m1 m0 c2 3.3 m f c1 1 m f 100pf 100pf 100pf latch dce/dte m2 m1 m0 latch dce/dte + figure 13. typical application using the ltc1344
10 ltc1344 typical applicatio n s n u ltc1343 1 2 4 3 8 5 6 7 9 10 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 19 18 17 12 13 14 15 16 40 23 20 22 11 25 ctrl latch invert 423 set dce m2 m1 m0 r2 r3 r4 r1 100k ll a txd a txd b scte a scte b tm a rxd a rxd b rxc a rxc b rxc a rxc b rxd a rxd b tm a rts a rts b dtr a dtr b dcd a dcd b dsr a dsr b cts a cts b dcd a dcd b dtr a dtr b rts a rts b 18 dte dce 20 22 23 24 1 m0 m1 m2 dce/ dte 13 12 11 38 c6 100pf c7 100pf 19 17 18 15 16 10 9 7 6 4 5 2 44 c2 1 m f c4 3.3 m f c10 1 m f c13 3.3 m f c5 1 m f c1 1 m f 43 42 41 14 v ee v cc v cc 5v 2 14 24 11 15 12 17 9 3 16 25 7 1 4 19 20 23 8 10 6 22 5 13 21 1344 ta02 db-25 connector ltc1344 c8 100pf 21 r1 c3 1 m f gnd lb v cc v cc v cc ec 24 ltc1343 1 2 4 3 8 5 6 7 9 10 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 19 18 17 12 13 14 15 16 40 23 20 22 11 25 ctrl latch invert 423 set dce m2 m1 m0 r2 r3 r4 r2 100k 44 c12 1 m f c9 1 m f 43 42 41 c11 1 m f gnd lb ec r1 dte_ll/dce_tm dte_txd/dce_rxd dte_sct/dec_rxc dte_txc/dce_txc dte_rxc/dce_scte dte_rxd/dce_txd dte_tm/dce_ll dte_rl/dce_rl dte_rts/dce_cts dte_dtr/dce_dsr dte_dcd/dce_dcd dte_dsr/dce_dtr dte_cts/dce_rts lb latch dce/dte m2 m1 m0 sgnd shield rl a cts a cts b dsr a dsr b rl a charge pump charge pump d1 d2 d3 d4 d1 d2 d3 d4 txc a txc b scte a scte b txd a txd b ll a txc a txc b 24 latch + + controller selectable multiprotocol dte port with db-25 connector
11 ltc1344 typical applicatio n s n u cable selectable multiprotocol dte port with db-25 connector ltc1343 1 2 4 3 8 5 6 7 9 10 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 19 18 17 12 13 14 15 16 40 23 20 22 11 25 ctrl latch invert 423 set dce m2 m1 m0 r2 r3 r4 r1 100k txd a txd b scte a scte b rxd a rxd b rxc a rxc b rxc a rxc b rxd a rxd b rts a rts b dtr a dtr b dcd a dcd b dsr a dsr b cts a cts b dcd a dcd b dtr a dtr b rts a rts b dte dce 20 22 23 24 1 m0 m1 m2 dce/ dte 13 12 11 38 c6 100pf c7 100pf 19 17 18 15 16 10 9 7 6 4 5 2 44 c2 1 m f c4 3.3 m f c10 1 m f c13 3.3 m f c5 1 m f c1 1 m f 43 42 41 14 v ee v cc v cc 5v 2 14 24 11 15 12 17 9 3 16 7 1 4 19 20 23 8 10 6 22 5 13 25 21 18 1344 ta03 db-25 connector ltc1344 c8 100pf r1 c3 1 m f gnd lb v cc v cc v cc v cc v cc v cc ec 24 ltc1343 1 2 4 3 8 5 6 7 9 10 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 19 18 17 12 13 14 15 16 40 23 20 22 11 25 ctrl latch invert 423 set dce m2 m1 m0 r2 r3 r4 r2 100k 44 c12 1 m f c9 1 m f 43 42 41 c11 1 m f gnd lb ec r1 dte_txd/dce_rxd dte_scte/dec_rxc dte_txc/dce_txc dte_rxc/dce_scte dte_rxd/dce_txd dte_rts/dce_cts dte_dtr/dce_dsr dte_dcd/dce_dcd dte_dsr/dce_dtr dte_cts/ dce_rts lb sgnd shield cts a cts b dsr a dsr b charge pump charge pump d1 d2 d3 d4 txc a txc b scte a scte b txd a txd b txc a txc b r5 10k r4 10k dce/dte m1 m0 v cc v cc d1 d2 d3 d4 24 r3 10k v cc cable wiring for mode selection mode pin 18 pin 21 v.35 pin 7 pin 7 eia-530, rs449, nc pin 7 v.36, x.21 rs232 pin 7 nc cable wiring for dte/dce selection mode pin 25 dte pin 7 dce nc 21 latch + + information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
12 ltc1344 ? linear technology corporation 1996 1344fa lt/tp 0300 2k rev a ? printed in usa package descriptio n u g package 24-lead plastic ssop (0.209) (ltc dwg # 05-08-1640) g24 ssop 1098 0.13 ?0.22 (0.005 ?0.009) 0 ?8 0.55 ?0.95 (0.022 ?0.037) 5.20 ?5.38** (0.205 ?0.212) 7.65 ?7.90 (0.301 ?0.311) 1234 5 6 7 8 9 10 11 12 8.07 ?8.33* (0.318 ?0.328) 21 22 18 17 16 15 14 13 19 20 23 24 1.73 ?1.99 (0.068 ?0.078) 0.05 ?0.21 (0.002 ?0.008) 0.65 (0.0256) bsc 0.25 ?0.38 (0.010 ?0.015) note: dimensions are in millimeters dimensions do not include mold flash. mold flash shall not exceed 0.152mm (0.006") per side dimensions do not include interlead flash. interlead flash shall not exceed 0.254mm (0.010") per side * ** dimensions in inches (millimeters) unless otherwise noted. related parts part number description comments ltc1334 single supply rs232/rs485 transceiver 2 rs485 dr/rx or 4 rs232 dr/rx pairs ltc1343 multiprotocol serial transceiver software selectable mulitprotocol interface ltc1345 single supply v.35 transceiver 3 dr/3 rx for data and clk signals ltc1346a dual supply v.35 transceiver 3 dr/3 rx for data and clk signals ltc1344a multiprotocol cable terminator, pin compatible to ltc1344 allows separate rs449 mode ltc1543 multiprotocol serial transceiver 3 dr/3 rx for data and clk signals ltc1544 multiprotocol serial transceiver 4 dr/4 rx for control signals and ll ltc1545 multiprotocol serial transceiver 5 dr/5 rx for control signals, ll, rl amd tm linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com

▲Up To Search▲

Price & Availability of LTC1344-15

	To Download LTC1344-15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .